As is well known, FED technology operates on the principle of cathodoluminescent phosphors being excited by cold cathode field emission electrons. FIG. 1 is a simplified illustration of a representative portion of a prior art FED 10. In general, the FED 10 comprises a cathode assembly 6 and an anode assembly 8 separated from each other by spacers 4.
The cathode assembly 6 is typically manufactured using conventional photolithographic processes to form successively defined features on a substrate or base plate 12. In general, a conductive emitter electrode structure 14 is first formed on the substrate 12. Next, a resistive layer 15 is deposited over the conductive structure 14. A pattern of spaced-apart conical cold cathode emitter tips or micropoints 18 is then formed on the substrate 12, followed by a dielectric structure 20 and a conductive or extraction grid structure 22.
The substrate or base plate 12 is typically formed of glass. The conductive structure 14 may be formed of a metal. The micropoints 18 may be constructed of a number of materials such as, e.g., silicon or molybdenum.
The conductive structure 14 with the covering resistive layer 15 encircles the emitter tips 18 of a pixel group (described below). The portions of the conductive structure 14 shown in FIG. 1 are thus electrically connected and form a column line, which is part of an addressable matrix as will be described below.
The resistive layer 15 comprising, e.g., amorphous silicon, covers the top and sides of the conductive structure 14. As shown, the outer sides of the base of each conical micropoint 18 are in contact with the resistive layer covering the conductive structure 14. The resistive layer 15 separates the conductive structure 14 from the micropoints 18 and helps prevent damage to the tips of the micropoints 18.
After the micropoints 18 have been formed on the base plate 12, a dielectric layer is deposited over the micropoints 18 and the resistive layer 15. The dielectric layer, which is later formed into the dielectric structure 20, may comprise silicon dioxide or other materials. Next, a conductive layer is deposited over the dielectric layer. This conductive layer, which is later formed into the extraction grid structure 22, may be made from a variety of materials including chromium, molybdenum and doped polysilicon. Then, using a photolithography/etch process, the dielectric layer and the conductive layer are etched to form the dielectric and extraction structures 20, 22, respectively, which surround, but are spaced away from, the micropoints 18 as shown in FIG. 1.
The extraction grid structure 22 forms a low potential anode that is used to extract electrons from the micropoints 18. The extraction structure has a grid construction comprising multiple row lines that are orthogonal to the column lines formed by the conductive structure 14. The row and column lines are part of the addressable matrix as described below.
The anode assembly 8 usually has a transparent (e.g., glass) substrate 24 and a transparent conductive layer 26 formed over the substrate 24 (on the side facing cathode assembly 6). A black matrix grill 25 is formed over the conductive layer 26 to define pixel regions 28, in which a cathodoluminescent coating is deposited.
The anode assembly 8 is typically manufactured using conventional photolithography processes to form successively defined features on the lower (as shown in FIG. 1) surface of the transparent substrate 24, starting with transparent conductive layer 26. The next features usually formed are the spacers 4, which project downwardly (e.g., about 150 microns) from conductive layer 26. The black matrix grill 25 is then formed defining the pixel regions 28, in which phosphor material is deposited.
When assembled, the anode assembly 8 is positioned a predetermined distance from the cathode assembly 6 (and from micropoints 18) by the spacers 4.
A power supply 30 is electrically coupled to the conductive layer 26 of the anode assembly 8 and to the conductive structure 14 (at the base of the micropoints 18) and the conductive grid structure 22 of the cathode assembly 6. A vacuum in the space between cathode assembly 6 and anode assembly 8 facilitates travel of electrons emitted from the micropoints 18 towards the pixel regions 28 to impact the pixel regions. The emitted electrons strike the cathodoluminescent coating in the pixel regions 28, which emits light to form a video image on a display screen formed by the anode assembly 8.
The visible display of the FED 10 is normally arranged as a matrix of pixels, one of which (single pixel 32) is shown in FIG. 1. Each pixel in the display is typically associated with a group of micropoint emitters, with all emitters in a group being dedicated to controlling the brightness of their associated pixel. For example, FIG. 1 shows a single pixel 32, with the pixel being associated with emitter tips 18. For convenience of illustration, FIG. 1 shows a line of four emitters as being associated with the single pixel 32. Pixel 32 could be a single pixel of a black and white display or a single red, green, or blue dot associated with a single pixel of a color display.
The row lines of the extraction grid structure 22 and the column lines of the emitter electrode structure 14 form an addressing matrix for selectively activating pixels. Normally, the row and column lines are arranged so that the emitters associated with one pixel can be controlled independently of all other emitters in the display and so that all emitters associated with a single pixel are controlled in unison. In operation, a row signal activates a single conductive row line within the extraction grid structure 22, while a column signal activates a conductive column line within the emitter base electrode structure 14. At the intersection of an activated column and an activated row, a grid-to-emitter voltage differential sufficient to induce field emission will exist, causing illumination of a respective pixel.
Conventional photolithography processes are typically used to fabricate the various structures (e.g., the conductive structure 14) of the FED 10.
It has been found in prior art FEDs that the addressing column line conductive structure 14 sometimes electrically shorts to the row line conductive structure 22. Such electrical shorting degrades the quality of the display and can even make the FED inoperative. The shorting is believed to result from manufacturing flaws in FEDs. For example, intrinsic defects in the dielectric structure 20 may effectively form conductive paths between the column addressing line and the grid. In addition, variations in the substrate and grid surfaces that cause the surfaces to be closer than intended may also cause shorting. A need, therefore, exists for an improved FED construction that significantly reduces the possibility of electrical shorting between column and row lines.